This invention relates to operational amplifiers, and in particular to operational amplifiers having enhanced-gain output stages.
The high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC) for telecommunications use require very short linear adaptation times in order to drive large capacitive switching loads and attain high resolution.
Single-stage structures are needed to obtain a very wide band and fast adaptation. Major sources of problems with such structures are the low DC gain provided by conventional single-stage amplifiers in a cascode configuration and the large amount of power dissipated by Class A amplifiers.
To obviate the problem of a low DC gain, several structures with an enhanced-gain output stage have been proposed. An article xe2x80x9cA CMOS Operational Amplifier with Fully-Differential Gain-Enhancementxe2x80x9d by Lloyd and Lee, IEEE Trans. On Circuits and Systems, Vol. 41, No. 3, March 1994, pages 241-243, discloses an efficient way of enhancing gain without incurring losses in the rail-to-rail output operation.
One problem with that structure is its Class A mode of operation resulting in large power consumption. Another problem is the fixed output bias. Both are constraints that limit the adaptability of the output stage for a given bias current. No efficient way of obtaining a dynamic bias with this cascode structure has been found. In addition, the buffer states employed with the enhanced-gain stages comprise differential PMOS stages and a single NMOS stage. This restricts the phase margin achievable for a given bandwidth, due to PMOS transistors being slower than NMOS transistors at the same bias current.
A single-stage Class AB structure directed to obviate the problem of a high consumption is disclosed in Castello and Gray, xe2x80x9cA High Performance Micropower Switched Capacitor Filterxe2x80x9d, IEEE J. Solid State Circuits, Vol. SC-20, Dec. 1985, pages 1122-1132. This article discloses a highly efficient way of obtaining Class AB operability and adaptative bias. However, no provision for boosting is given.
One embodiment of the invention concerns an operational amplifier providing both gain enhancement and adaptative biasing of the output stage.
The operational amplifier includes: a first output terminal; a main differential stage having first and second differential inputs and a first differential output stage; and a first output stage which is boosted and biased adaptatively to couple the first differential output stage to the output terminal. The first boosted output stage includes a first output transistor having a control terminal, a first terminal coupled to the first output terminal, and a second terminal; and a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to adaptatively bias the first boosted output stage, and an output coupled to the control terminal of the first output transistor.
Another embodiment of the invention concerns an operational amplifier which includes a first output terminal and a main differential stage having first and second inputs and first and second differential outputs. A first boosted output stage couples the output of the first differential stage to the output terminal and includes a first differential output stage having first and second N-channel transistors connected together into a differential configuration. A second boosted output stage couples the output of the second differential stage to the first output terminal and includes a second differential output stage having third and fourth N-channel transistors connected together into a differential configuration.
A further embodiment of the invention concerns an operational amplifier which includes a first output terminal; a main differential stage having first and second differential inputs, and a first differential output stage; and a first boosted output stage coupling the first differential output stage to the output terminal. The first boosted output stage includes a first output transistor having a control terminal, a first terminal coupled to the first output terminal, and a second terminal; and a first output amplifier having first and second N-channel transistors connected into a differential configuration, and a P-channel transistor having a control terminal coupled to the second terminal of the first output transistor, a first terminal whereat shifted level bias is produced, and a second terminal coupled to a first voltage reference. The first N-channel transistor has a control terminal coupled to a first bias voltage reference, and the second N-channel transistor has its control terminal coupled to the first terminal of the P-channel transistor.